1. Technical Field
The present invention relates generally to communications equipment, and more particularly, to a clock signal recovery circuit preferably implemented in a receiver of a universal serial bus (USB) and a method for recovering a clock signal.
2. Description of Related Art
A universal serial bus (hereinafter referred to as USB) is an interface standard for peripheral devices of a personal computer (PC). The implementation of USB affords integration of a plurality of interfaces for various peripheral equipment, thereby allowing a PC to be readily connected to a plurality of peripheral equipment at low cost. Consequently, USB has been employed for use with many types of PCs and peripheral equipment.
A USB transmitter and a USB receiver (usually implemented in a single module, i.e., a USB transceiver) are necessary to communicate through the USB. In general, the same clock signal is used in the USB transmitter and the USB receiver. Thus, to recover data transmitted from the USB transmitter, the USB receiver must recover a clock signal having the same frequency and phase as the clock signal of the USB transmitter.
Conventional methods for recovering a clock signal typically include an analog method and a digital method. By way of example, FIG. 1 illustrates a conventional analog clock signal recovery circuit. The circuit comprises an analog phase locked loop (hereinafter referred to as PLL) circuit. The PLL circuit shown in FIG. 1 comprises a phase detector 12, a loop filter 14, and a voltage controlled oscillator (VCO) 16.
A recovery clock (RCCK) signal generated by a conventional PLL circuit is a signal having an arbitrary phase at the beginning of an operation. The phase of the RCCK signal is controlled by a control voltage (VCON) generated by the phase detector 12 and the loop filter 14. The VCO 16 generates the RCCK signal having a phase that is varied by the control voltage VCON. The RCCK signal is fed back to the phase detector 12 so that a phase of the RCCK signal may be compared with the phase of received data (R_DATA). The above operation will be repeated until the phases of the RCCK signal and the R_DATA are synchronized, at which time the PLL circuit is “locked.”
One disadvantage associated with the conventional PLL circuit is the time delay for recovering the RCCK signal synchronized with the R_DATA. To combat this delay associated with the conventional analog clock signal recovery method, a digital clock signal recovery method can be implemented to obtain a fast synchronous time. In general, with this method, a delay locked loop (hereinafter, referred to as DLL) circuit is used for controlling phase via a digital delay line. One disadvantage associated with the DLL method is that the DLL circuit comprises a multistage digital delay line and, consequently, the DLL circuit is large and consumes much power.
As communication technology has progressed, the USB standard has also progressed. Currently, the USB 2.0 standard has been standardized. USB 2.0 requires the USB receiver to recover a clock signal within a short preamble, that is, within a 4-clock period. Thus, a clock signal can be recovered within a short time (4-clock period). Accordingly, a clock signal recovery circuit that is small in size, consumes little power, and that can recover a clock signal within a short period is highly desirable.